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STA333BW
2.1-channel high-efficiency digital audio system
Preliminary Data
Features
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Wide supply voltage range (4.5 to 20 V) 3 power output configurations - 2 channels of ternary PWM (stereo mode) (2 x 20 W @ 8 , 18 V). - 3 channels - left, right using binary and LFE using ternary PWM (2.1 mode) (2 x 9 W + 1 x 20 W @ 2 x 4 , 1 x 8 , 18 V) - 2 channels of ternary PWM (2 x 20 W) + stereo line out ternary 2.1 channels of 24-bit DDX(R) 100 dB SNR and dynamic range Selectable 32 KHz to 192 KHz input sample rates I2C control with selectable device address Digital gain/attenuation +48 dB to -80 dB in 0.5 dB steps Soft volume update Individual channel and master gain/attenuation Dual independent limiters/compressors Dynamic range compression or anti-clipping modes AutomodesTM - 15 preset crossover filters - 2 preset anti-clipping modes - Preset nighttime listening mode Individual channel and master soft and hard mute Independent channel volume and DSP bypass Automatic zero-detect mute
PowerSSO36 slug down
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Automatic invalid input detect mute 2-channel I2S input data interface Input and output channel mapping 4 x 28-bit user programmable biquads (EQ) per channel Bass/treble tone control DC blocking selectable high-pass filter Selectable de-emphasis Sub channel mix into left and right channels Advanced AM interference frequency switching and noise suppression modes Selectable high or low bandwidth noise shaping topologies Variable max power correction for lower fullpower THD Selectable clock input ratio 96 kHz internal processing sample rate, 24 to 28-bit precision Thermal overload and short-circuit protection embedded Video application supports 576 x fs input mode PSSO-36 slug down package, RoHS.
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Table 1. Device summary
Order codes STA333BW STA333BW13TR Package PowerSSO36 slug down PowerSSO36 slug down Packing Tube Tape and reel
July 2007
Rev 2
1/64
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STA333BW
Contents
1 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connections and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6.1 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 5
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 5.1.2 5.1.3 5.1.4 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 5.3
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 5.3.2 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.1 5.4.2 5.4.3 5.4.4 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/64
STA333BW 5.4.5 5.4.6
Contents Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2
Configuration register B (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3
Configuration register C (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3.1 6.3.2 6.3.3 DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DDX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 28 Over-current warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 29
6.4
Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 30 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Miami ModeTM enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5
Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 32 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/64
Contents 6.5.8
STA333BW Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.6
Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 38 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.7
Volume control registers (0x06 to 0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.8
Auto mode registers (0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.8.1 6.8.2 6.8.3 6.8.4 AutoMode register 1 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AutoMode register 2 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.9
Channel configuration registers ( 0x0E to 0x10) . . . . . . . . . . . . . . . . . . . 43
6.9.1 6.9.2 6.9.3 6.9.4 6.9.5 6.9.6 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.10 6.11
Tone control register (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.10.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Dynamics control registers (0x12 to 0x15) . . . . . . . . . . . . . . . . . . . . . . . . 46
6.11.1 6.11.2 6.11.3 6.11.4 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.12
User-defined coefficient control registers (0x16 to 0x26) . . . . . . . . . . . . . 50
6.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/64
STA333BW 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9
Contents Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.12.21 Over-current post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.13 6.14 6.15 6.16
Variable max power correction registers (0x27 to 0x28) . . . . . . . . . . . . . 57 Variable distortion compensation registers (0x29 to 0x2A) . . . . . . . . . . . 57 Fault detect recovery constant registers (0x2B to 0x2C) . . . . . . . . . . . . . 58 Device status register (0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.1 7.2 7.3 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8 9 10
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5/64
List of tables
STA333BW
List of tables
Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics power section VCC= 18 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 C, RL = 8 unless otherwise specified13 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 25 Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 26 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AutoMode gain compression/limiters selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AutoMode AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 45 Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter attack threshold as a function of LxAT bits (AC-Mode). . . . . . . . . . . . . . . . . . . . . . 49 Limiter release threshold as a function of LxRT bits (AC-Mode). . . . . . . . . . . . . . . . . . . . . 49 Limiter attack threshold as a function of LxAT bits (DRC-Mode). . . . . . . . . . . . . . . . . . . . . 50 Limiter release threshold as a as a function of LxRT bits (DRC-Mode).. . . . . . . . . . . . . . . 50 RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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STA333BW
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection PowerSSO-36 (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Processing data flow 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Processing data flow 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STA333BW output mapping scheme.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.0 channels (OCFG='00') PWM slots.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.1 channels (OCFG='01') PWM slots.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.1 channels (OCFG='10') PWM slots.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PLL application scheme.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Double layer PCB Rth j-amb with 2 GND copper area and with 16 via holes . . . . . . . . . . . . 61 PSSO36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PowerSSO-36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 62
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Overview
STA333BW
1
Overview
The STA333BW is an integrated circuit comprising digital audio processing, digital amplifier control, and DDX-power output stage to create a high-power single-chip DDX(R) solution with high-quality, high-efficiency and all digital amplification. The STA333BW is part of the Sound TerminalTM family that provides full digital audio streaming to the speaker, thereby offering cost effectiveness, low power dissipation and sound enrichment. The IC power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2 x 9 W + 1 x 20 W of power output. Two channels can be provided by two full-bridges, providing up to 2 x 20 W of power. The IC can also be configured as a 2.1 channels with 2 x 20 W provided by the device and external power for DDX(R) power drive. Also provided in the STA333BW are a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. AutomodesTM enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes Auto Volume loudness, preset volume curves and preset EQ settings. New advanced AM radio interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I2S format. Three channels of DDX(R) processing are provided. This high-quality conversion from PCM audio to DDX patented tri-state PWM switching waveform provides over 100 dB SNR and dynamic range. Figure 1. Block diagram
I2 C I2 S interface
Protection current/thermal Channel 1A
Volume control
Power control DDX
Logic
Channel 1B
Channel 2A
Regulators PLL Bias Digital DSP Power Channel 2B
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STA333BW
Connections and pin description
2
2.1
Connections and pin description
Connection diagram
Figure 2. Pin connection PowerSSO-36 (Top view)
GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A GND_REG VDD CONFIG OUT3B/DDX3B OUT3A/DDX3A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD_DIG GND_DIG SCL SDA INT_LINE RESET SDI LRCKI BICKI XTI PLL_GND FILTER_PLL VDD_PLL PWRDN GND_DIG VDD_DIG TWARN/OUT4B EAPD/OUT4A
D05AU1638
2.2
Pin description
Table 2.
Pin 1 2 3 4 5 6 7 8 9 10
Pin description
Type GND I I I/O I/O O GND Power O O Name GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B Substrate ground I2C select address This pin must be connected to ground Internal reference at Vcc-3.3 V Internal Vcc reference Output half bridge 2B Power negative supply Power positive supply Output half bridge 2A Output half bridge 1B Description
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Connections and pin description Table 2.
Pin 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
STA333BW
Pin description (continued)
Type Power GND I/O GND Power I O O O I Power GND I Power I GND I I I I I O I/O I GND Power Name VCC1 GND1 OUT1A GND_REG VDD CONFIG OUT3B/DDX3B OUT3A/DDX3A EAPD/OUT4A TWARN/OUT4B VDD_DIG GND_DIG PWRDN VDD_PLL FILTER_PLL GND_PLL XTI BICKI LRCKI SDI RESET INT_LINE SDA SCL GND_DIG VDD_DIG Description Power positive supply Power negative supply Output half bridge 1A Internal ground reference Internal 3.3 V reference voltage Paralleled mode command PWM out CH3B, external bridge PWM out CH3A, external bridge Power down for external bridge Thermal warning from external bridge Digital supply voltage Digital groun Power down Positive supply for PLL Connection to PLL filter Negative supply for PLL PLL input clock I2S serial clock I2S left/right clock I2S serial data channels 1 and 2 Reset Fault interrupt: 0: fault detected in the power bridge, 1: normal operation) I2C serial data I2C serial clock Digital ground Digital supply voltage
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STA333BW
Connections and pin description
2.3
Thermal data
Table 3. Thermal data
Parameter Rth j-case Tth-sdj Tth-w Tth-sdh Rth j-amb Thermal resistance junction-case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis Thermal resistance junction-ambient
(1)
Min.
Typ.
Max. 1.5
Unit C/W C C C
150 130 20
1. See Section 8: Package thermal characteristics on page 61 for details.
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Electrical specifications
STA333BW
3
3.1
Electrical specifications
Absolute maximum ratings
Stresses beyond those listed below in Table 4 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Section 3.2: Recommended operating conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In real applications, power supplies with nominal-rated voltages within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for short times when no or very low current is being sunk (for example, amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are never exceeded. Table 4.
Symbol Vcc
Absolute maximum ratings
Parameter Power supply voltage (VCC1, VCC2) Min -0.3 -0.3 -0.3 0 -40 Typ Max 23 4 4 150 150 Unit V V V C C
VDD_DIG Digital supply voltage VDD_PLL PLL supply voltage Top Tstg Operating junction temperature Storage temperature
3.2
Recommended operating conditions
Table 5.
Symbol Vcc
Recommended operating condition
Parameter Power supply voltage (VCC1, VCC2) Min 4.5 2.7 2.7 0 3.3 3.3 Typ Max 20 3.6 3.6 70 Unit V V V C
VDD_DIG Digital supply voltage VDD_PLL PLL supply voltage Tamb Ambient temperature
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STA333BW
Electrical specifications
3.3
Symbol Iil Iih Vil Vih Vol Voh Ipu Rpu
Electrical specifications - digital section
Parameter Low level input current , no pull-up resistor High level input current, no pull-down resistor Low level input voltage High level input voltage Low level output voltage High level output voltage Pull-up current Equivalent pull-up resistance Iol = 2 mA Ioh = 2 mA 0.8 * VDD_DIG -25 66 50 125 0.8 * VDD_DIG 0.4 * VDD_DIG Conditions Vi=0 V Vi = VDD_DIG = 3.6 V Min -10 -10 Typ Max 10 10 0.2 * VDD_DIG Unit A A V V V V A k
3.4
Table 6.
Symbol
Electrical specifications - power section
Electrical characteristics power section VCC= 18 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 C, RL = 8 unless otherwise specified
Parameter Output power BTL THD = 10% 20 THD = 1% Output power SE RL = 4 THD = 10% 7 W 9 180 95 95 10 8 15 10 10 4.5 15 30 18 18 18 250 m % % A ns ns ns ns V Conditions THD = 1% Min Typ 16 W Max Unit
Po
RdsON gP gN Idss ILDT IHDT tr tf Vcc
Power P-channel/N-channel MOSFET (total bridge) Power P-channel RdsON matching Power N-channel RdsON matching Power P-channel/N-channel leakage ldss Low-current dead time (static) High-current dead time (dynamic) Rise time Fall time Supply voltage operating voltage
ld = 1.5 A ld = 1.5 A ld = 1.5 A VCC = 20 V Resistive load(1) Iload = 1.5 A(1) Resistive load(1) Resistive load(1)
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Electrical specifications Table 6.
Symbol
STA333BW
Electrical characteristics power section (continued) VCC= 18 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 C, RL = 8 unless otherwise specified
Parameter Conditions Min Typ 0.1 Max 1 Unit mA
Supply current from Vcc in power PWRDN = 0 down IVCC Supply current from Vcc in operation Supply current DDX processing (reference only) Overcurrent limit Short circuit protection Under-voltage protection Output minimum pulse width Dynamic range Signal to noise ratio, ternary mode Signal to noise ratio binary mode PSSR Power supply rejection ratio DDX stereo mode, <5 kHz VRIPPLE = 1 V RMS Audio input = dither only DDX stereo mode, Po=1 W f = 1 kHz DDX stereo mode, <5 kHz One channel driven @ 1 W Other channel measured Po = 2 x 20 W, 8 Po = 2 x 9 W @ 4 , 1 x 20 W @8 No load 20 PCM input signal = -60 dBFS, Switching frequency = 384 kHz No LC filters Internal clock = 49.152 MHz
(2)
30
mA
IVDD Ilim Isc UVL tmin DR
80 2.2 2.7 3.0 3.6 3.5 30 100 100 4.3 60 4.0
mA A A V ns dB dB dB dB
Hi-Z output
SNR
A-Weighted 90 80
THD+N
Total harmonic distortion + noise
0.2
%
XTALK
Crosstalk Peak efficiency, DDX mode
80 90
dB
Peak efficiency,binary modes
1. Refer to Figure 4: Test circuit 1.
% 87
2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled refer to the Isc.
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STA333BW
Electrical specifications
3.5
Power-on sequence
Figure 3. Power-on sequence
VCC VDD_DIG XTI Reset I 2C PWDN
Don't care
TR
TC
Don't care
CMD0
CMD1
CMD2
Referring to Figure 3 above: TR = mimimum time between XTI master clock stable and reset removal: 1 ms, TC = minimum time between reset removal and I2C program sequence start: 1 ms. Note: Note: Clock stable means: fmax - fmin < 1 MHz. VCC > VDD_DIG must be guaranteed at all times.
3.6
3.6.1
Testing
Functional pin status
Table 7.
Pin name PWRDN PWRDN TWARN TWARN EAPD EAPD
Functional pin status
Number 23 23 20 20 19 19 Logic value 0 1 0 1 0 1 Low-power mode Normal operation Temperature warning from external power stage Normal operation Low-power operation for power stage. All internal regulators are switched off Normal operation IC status
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Electrical specifications Figure 4. Test circuit 1
OUTxY Vcc (3/4)Vcc Low-current dead time = MAX(DTr, DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50% M58 INxY M57 gnd OUTxY DTr R8 V67 vdc = Vcc/2 DTf
STA333BW
+ -
Figure 5.
Test circuit 2
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC
Duty cycle=A
DTout(A) M58 Q1 OUTA Rload=4 L67 10 C69 470nF DTout(B) L68 10 C70 470nF Q2 OUTB M64
Duty cycle=B
DTin(A) INA
DTin(B) INB
Iout=1.5A M57 Q3
Iout=1.5A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
D06AU1651
16/64
STA333BW
Processing data paths
4
Processing data paths
Here are some diagrams that represent the data processing paths inside STA333BW. The first 2x oversampling FIR filter allows 2fs audio processing. Then a selectable high-pass filter removes the DC level. Four biquad filters allow a full equalization system. A final crossover filter is present that can alternatively be used as a fifth biquad stage (see the IIC registers for this specific usage). A pre scaler and a final post scaler provide full control over the signal dynamics before and after the filtering stages, respectively. A mixer function is also available. Figure 6.
Sampling frequency=Fs
Processing data flow 1
Sampling frequency=2xFs
x2 FIR over sampling
PreScale
Hi-Pass Filter
Biquad #1
Biquad #2
Biquad #3
Biquad #4
DeEmphasis
Bass
Treble
L
If HPB=0 If DEMP=0 From I2S input interface
User-Defined Filters
If C1TCB=0 BTC: Bass Boost/Cut TTC: Treble Boost/Cut
If DSPB=0 and C1EQBP=0
x2 FIR over sampling
PreScale
Hi-Pass Filter
Biquad #1
Biquad #2
Biquad #3
Biquad #4
DeEmphasis
Bass
Treble
R
If HPB=0 If DEMP=0
User-Defined Filters
If C2TCB=0 BTC: Bass Boost/Cut TTC: Treble Boost/Cut
If DSPB=0 and C2EQBP=0
Figure 7.
Processing data flow 2
C1Mx1
L R
+
C1Mx2
Hi-Pass XO Filter
Vol And Limiter
Post scale
C2Mx1
+
C2Mx2
Hi-Pass XO Filter
Vol And Limiter
Post scale
C3Mx1
+
C3Mx2
Lo-Pass XO Filter
Vol And Limiter
Post scale
User-Defined Mix Coefficients
Crossover Frequency determined by XO Setting User Defined If XO=0000
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I2C bus specification
STA333BW
5
I2C bus specification
The STA333BW supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. STA333BW is always a slave device in all of its communications. It supports up to 400 kb/sec rate (fast-mode bit rate). STA333BW I2C is a slave only interface.
5.1
5.1.1
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.
5.1.2
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
5.1.3
Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA333BW and the bus master.
5.1.4
Data input
During the data input the STA333BW samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
5.2
Device addressing
To start communication between the master and the STA333BW, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode. The seven most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA333BW the I2C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1. The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA333BW identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.
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STA333BW
I2C bus specification
5.3
Write operation
Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA333BW again responds with an acknowledgement.
5.3.1
Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the STA333BW. The master then terminates the transfer by generating a STOP condition.
5.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer.
5.4
5.4.1
Read operation
Current address byte read
Following the START condition the master sends a device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
5.4.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
5.4.3
Random address byte read
Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA333BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
5.4.4
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
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I2C bus specification
STA333BW
5.4.5
Figure 8.
BYTE WRITE
Write mode sequence
Write mode sequence
ACK DEV-ADDR START RW ACK ACK SUB-ADDR RW DATA IN ACK DATA IN STOP SUB-ADDR ACK DATA IN STOP ACK ACK
MULTIBYTE WRITE START
DEV-ADDR
5.4.6
Figure 9.
CURRENT ADDRESS READ START
Read mode sequence
Read mode sequence
ACK NO ACK
DEV-ADDR RW ACK
DATA STOP ACK SUB-ADDR DEV-ADDR ACK DATA NO ACK
RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START
DEV-ADDR
RW RW= ACK HIGH DEV-ADDR DATA
START ACK DATA
RW ACK DATA NO ACK
STOP
STOP ACK ACK SUB-ADDR RW START DEV-ADDR RW ACK DATA ACK DATA ACK DATA STOP NO ACK
SEQUENTIAL RANDOM READ START
DEV-ADDR
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STA333BW
Register description
6
Table 8.
Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
Register description
Register summary
Name ConfA ConfB ConfC ConfD ConfE ConfF Mute/LOC Mvol C1Vol C2Vol C3Vol Auto1 Auto2 Auto3 C1Cfg C2Cfg C3Cfg Tone L1ar L1atrt L2ar L2atrt Cfaddr B1cf1 B1cf2 B1cf3 B2cf1 B2cf2 B2cf3 A1cf1 A1cf2 A1cf3 C1B23 C1B15 C1B7 C2B23 C2B15 C2B7 C3B23 C3B15 C3B7 C1B22 C1B14 C1B6 C2B22 C2B14 C2B6 C3B22 C3B14 C3B6 C1OM1 C2OM1 C3OM1 TTC3 L1A3 L1AT3 L2A3 L2AT3 C1OM0 C2OM0 C3OM0 TTC2 L1A2 L1AT2 L2A2 L2AT2 C1LS1 C2LS1 C3LS1 TTC1 L1A1 L1AT1 L2A1 L2AT1 CFA5 C1B21 C1B13 C1B5 C2B21 C2B13 C2B5 C3B21 C3B13 C3B5 C1LS0 C2LS0 C3LS0 TTC0 L1A0 L1AT0 L2A0 L2AT0 CFA4 C1B20 C1B12 C1B4 C2B20 C2B12 C2B4 C3B20 C3B12 C3B4 C1BO C2BO C3BO BTC3 L1R3 L1RT3 L2R3 L2RT3 CFA3 C1B19 C1B11 C1B3 C2B19 C2B11 C2B3 C3B19 C3B11 C3B3 C1VBP C2VBP C3VBP BTC2 L1R2 L1RT2 L2R2 L2RT2 CFA2 C1B18 C1B10 C1B2 C2B18 C2B10 C2B2 C3B18 C3B10 C3B2 BTC1 L1R1 L1RT1 L2R1 L2RT1 CFA1 C1B17 C1B9 C1B1 C2B17 C2B9 C2B1 C3B17 C3B9 C3B1 BTC0 L1R0 L1RT0 L2R0 L2RT0 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 C2B0 C3B16 C3B8 C3B0 C1EQBP C2EQBP C1TCB C2TCB XO3 XO2 D7 FDRB C2IM OCRB MME SVE EAPD LOC1 MV7 C1V7 C2V7 C3V7 ZDE ZCE PWDN LOC0 MV6 C1V6 C2V6 C3V6 MV5 C1V5 C2V5 C3V5 AMGC1 XO1 MV4 C1V4 C2V4 C3V4 AMGC0 XO0 AMAM2 AMAM1 AMAM0 AMAME D6 TWAB C1IM D5 TWRB DSCKE CSZ3 DRC DCCV ECLE D4 IR1 SAIFB CSZ2 BQL PWMS LDTE D3 IR0 SAI3 CSZ1 PSL AME BCLE C3M MV3 C1V3 C2V3 C3V3 D2 MCS2 SAI2 CSZ0 DSPB NSBW IDE C2M MV2 C1V2 C2V2 C3V2 D1 MCS1 SAI1 OM1 DEMP MPC OCFG1 C1M MV1 C1V1 C2V1 C3V1 D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 MMute MV0 C1V0 C2V0 C3V0
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Register description Table 8.
Addr 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30
STA333BW
Register summary (continued)
Name A2cf1 A2cf2 A2cf3 B0cf1 B0cf2 B0cf3 Cfud MPCC1 MPCC2 DCC1 DCC2 FDRC1 FDRC2 Status reserved reserved reserved MPCC15 MPCC14 MPCC7 DCC15 DCC7 FDRC15 FDRC7 PLLUL MPCC6 DCC14 DCC6 FDRC14 FDRC6 FAULT MPCC13 MPCC5 DCC13 DCC5 FDRC13 FDRC5 UVFAULT RO1BACT R01BEND MPCC12 MPCC4 DCC12 DCC4 FDRC12 FDRC4 OVFAULT R5BACT R5BEND R5BBAD D7 C4B23 C4B15 C4B7 C5B23 C5B15 C5B7 D6 C4B22 C4B14 C4B6 C5B22 C5B14 C5B6 D5 C4B21 C4B13 C4B5 C5B21 C5B13 C5B5 D4 C4B20 C4B12 C4B4 C5B20 C5B12 C5B4 D3 C4B19 C4B11 C4B3 C5B19 C5B11 C5B3 RA MPCC11 MPCC3 DCC11 DCC3 FDRC11 FDRC3 D2 C4B18 C4B10 C4B2 C5B18 C5B10 C5B2 R1 MPCC10 MPCC2 DCC10 DCC2 FDRC10 FDRC2 D1 C4B17 C4B9 C4B1 C5B17 C5B9 C5B1 WA MPCC9 MPCC1 DCC9 DCC1 FDRC9 FDRC1 TFAULT R2BACT D0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 W1 MPCC8 MPCC0 DCC8 DCC0 FDRC8 FDRC0 TWARN R1BACT
OCFAULT OCWARN R4BACT R4BEND R4BBAD R3BACT R3BEND R3BBAD
R2BEND R1BEND R2BBAD R1BBAD
6.1
Configuration register A (0x00)
D7 FDRB 0 D6 TWAB 1 D5 TWRB 1 D4 IR1 0 D3 IR0 0 D2 MCS2 0 D1 MCS1 1 D0 MCS0 1
6.1.1
Master clock select
Bit 0 1 2 R/W R/W R/W R/W RST 1 1 0 Name MCS0 MCS1 MCS2 Selects the ratio between the input I2S sample frequency and the input clock. Description
The STA333BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is:
" " "
32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
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STA333BW
Register description The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (iInput rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally Table 9. Input sampling rates
IR[1:0] 101 32, 44.1, 48 88.2, 96 176.4, 192 00 01 1X 576fs NA NA 100 128fs 64fs 32fs MCS[2:0] 011 256fs 128fs 64fs 010 384fs 192fs 96fs 001 512fs 256fs 128fs 000 768fs 384fs 192fs
Input sample rate Fs (kHz)
6.1.2
Interpolation ratio select
Bit 4:3 R/W R/W RST 00 Name IR[1:0] Description Selects internal interpolation ratio based on input I2S sample frequency
The STA333BW has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2 times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 10. IR bit settings as a function of input sample rate
IR[1:0] 00 00 00 01 01 10 10 1st stage interpolation ratio 2 times oversampling 2 times oversampling 2 times oversampling Pass-through Pass-through 2 times downsampling 2 times downsampling
Input sample rate Fs (kHz) 32 44.1 48 88.2 96 176.4 192
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Register description
STA333BW
6.1.3
Thermal warning recovery bypass
Bit 5 R/W R/W RST 1 Name TWRB Description 0: thermal warning recovery enabled 1: thermal warning recovery disabled
If the thermal warning adjustment is enabled (TWAB=0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative. If TWRB=0 and TWAB=0, then when a thermal warning disappears the -3 dB output limit is removed and the gain is added back to the system. If TWRB=1 and TWAB=0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset.
6.1.4
Thermal warning adjustment bypass
Bit 6 R/W R/W RST 1 Name TWAB Description 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled
The on-chip STA333BW power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 dB output limit (determined by TWOCL in Coeff RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0.
6.1.5
Fault detect recovery bypass
Bit 7 R/W R/W RST 0 Name FDRB Description 0: fault detect recovery enabled 1: fault detect recovery disabled
The on-chip STA333BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x29, 0x2A), then toggles it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1.
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STA333BW
Register description
6.2
Configuration register B (0x01)
D7 C2IM 1 D6 C1IM 0 D5 DSCKE 0 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0
6.2.1
Serial audio input interface format
Bit 0 1 2 3 R/W R/W R/W R/W R/W RST 0 0 0 0 Name SAI0 SAI1 SAI2 SAI3 Determines the interface format of the input serial digital audio interface. Description
6.2.2
Serial data interface
The STA333BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA333BW always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12. The SAI register (configuration register B (0x01), bits D3 to D0) and the SAIFB register (configuration register B (0x01), bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB-first. Available formats are shown in the tables and figure that follow.
6.2.3
Serial data first bit
SAIFB 0 1 MSB-first LSB-first Format
Table 11.
BICKI 32fs
Support serial audio input formats for MSB-first (SAIFB = 0)
SAI [3:0] 0000 0001 SAIFB 0 0 I2S 15-bit data Left/right-justified 16-bit data Interface format
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Register description Table 11.
BICKI
STA333BW Support serial audio input formats for MSB-first (SAIFB = 0) (continued)
SAI [3:0] 0000 0001 0010 SAIFB 0 0 0 0 0 0 0 0 0 0 0 0 I2 Interface format S 16 to 23-bit data
Left-justified 16 to 24-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data I2S 16 to 24-bit data Left-justified 16 to 24-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data
48fs 0110 1010 1110 0000 0001 0010 64fs 0110 1010 1110
Table 12.
BICKI 32fs
Supported serial audio input formats for LSB-first (SAIFB = 1)
SAI [3:0] 1100 1110 0100 0100 1000 1100 0001 0101 SAIFB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I2S 15-bit data Interface Format
Left/right-justified 16-bit data I2S 23-bit data I2S 20-bit data I2S 18-bit data LSB first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data
48fs 1001 1101 0010 0110 1010 1110
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STA333BW Table 12.
BICKI
Register description Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)
SAI [3:0] 0000 0100 1000 1100 0001 0101 64fs 1001 1101 0010 0110 1010 1110 1 1 1 1 1 1 Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data SAIFB 1 1 1 1 1 1 I S 24-bit data I2S 20-bit data I2S 18-bit data LSB first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data
2
Interface Format
6.2.4
Delay serial clock enable
Bit R/W RST Name Description 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices
5
R/W
0
DSCKE
6.2.5
Channel input mapping
Bit 6 7 R/W R/W R/W RST 0 1 Name C1IM C2IM Description 0: processing channel 1 receives Left I2S Input 1: processing channel 1 receives Right I2S Input 0: processing channel 2 receives Left I2S Input 1: processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel.
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Register description
STA333BW
6.3
Configuration register C (0x02)
D7 OCRB 1 D6 D5 CSZ3 0 D4 CSZ2 1 D3 CSZ1 0 D2 CSZ0 1 D1 OM1 1 D0 OM0 1
6.3.1
DDX power output mode
Bit 0 1 R/W R/W R/W RST 1 1 Name OM0 Selects configuration of DDX output. OM1 Description
The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. Table 13. Output modes
Output stage / mode Drop Compensation Discrete Output Stage, Tapered Compensation Full Power Mode Variable Drop Compensation (CSZx bits)
OM[1,0] 00 01 10 11
6.3.2
DDX compensating pulse size register
Bit 2 3 4 5 R/W R/W R/W R/W R/W RST 1 0 1 0 Name CSZ0 CSZ1 CSZ2 CSZ3 When OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 15 clock periods. Description
Table 14.
Table 6:
Compensating pulse size
Compensating Pulse Size 0 ns (0 tick) compensating pulse size 20 ns (1 tick) clock period compensating pulse size ... 300 ns (15 tick) clock period compensating pulse size
CSZ[3:0] 0000 0001 ... 1111
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STA333BW
Register description
6.3.3
Over-current warning detect adjustment bypass
Bit 7 R/W R/W RST 1 Name OCRB Description 0: over-current warning adjustment enabled 1: over-current warning adjustment disabled
The OCWARN input is used to indicate an over-current warning condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to eliminate the over-current warning condition. Once the over-current warning volume adjustment is applied, it remains in this state until reset is applied. The level of adjustment can be changed via the TWOCL (thermal warning/over current limit) setting which is address 0x37 of the user defined coefficient RAM.
6.4
Configuration register D (0x03)
D7 MME 0 D6 ZDE 1 D5 DRC 0 D4 BQL 0 D3 PSL 0 D2 DSPB 0 D1 DEMP 0 D0 HPB 0
6.4.1
High-pass filter bypass
Bit 0 R/W R/W RST 0 Name HPB Description Setting of one bypasses internal AC coupling digital high-pass filter
The STA333BW features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB=0, this filter is enabled.
6.4.2
De-emphasis
Bit 1 R/W R/W RST 0 Name DEMP 0: no de-emphasis 1: de-emphasis Description
Setting the DEMP bit enables de-emphasis on all channels
6.4.3
DSP bypass
Bit 2 R/W R/W RST 0 Name DSPB Description 0: normal operation 1: bypass of biquad and bass/treble functionality
Setting the DSPB bit bypasses the EQ functionality of the STA333BW.
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Register description
STA333BW
6.4.4
Post-scale link
Bit 3 R/W R/W RST 0 Name PSL Description 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value
Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster.
6.4.5
Biquad coefficient link
Bit 4 R/W R/W RST 0 Name BQL Description 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
6.4.6
Dynamic range compression/anti-clipping bit
Bit 5 R/W R/W RST 0 Name DRC Description 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.
6.4.7
Zero-detect mute enable
Bit 6 R/W R/W RST 1 Name ZDE Description Setting of 1 enables the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.
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STA333BW
Register description
6.4.8
Miami ModeTM enable
Bit 7 R/W R/W RST 0 Name MME Description 0: sub mix into left/right disabled 1: sub mix into left/right enabled
6.5
Configuration register E (0x04)
D7 SVE 1 D6 ZCE 1 D5 DCCV 0 D4 PWMS 0 D3 AME 0 D2 NSBW 0 D1 MPC 1 D0 MPCV 0
6.5.1
Max power correction variable
Bit 0 R/W R/W RST 0 Name MPCV Description 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient
6.5.2
Max power correction
Bit 1 R/W R/W RST 1 Name MPC Description Setting of 1 enables Power Bridge correction for THD reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA333BW power device at high power. This mode should lower the THD+N of a full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line-out channels.
6.5.3
Noise-shaper bandwidth selection
Bit 2 R/W R/W RST 0 Name NSBW 1: third order NS 0: fourth order NS Description
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Register description
STA333BW
6.5.4
AM mode enable
Bit 3 R/W R/W RST 0 Name AME Description 0: normal DDX operation. 1: AM reduction mode DDX operation
STA333BW features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83 dB in this mode, which is still greater than the SNR of AM radio.
6.5.5
PWM speed mode
Bit 4 R/W R/W RST 0 Name PWMS Description 0: normal speed (384 kHz) all channels 1: odd speed (341.3 kHz) all channels
6.5.6
Distortion compensation variable enable
Bit 5 R/W R/W RST 0 Name DCCV Description 0: uses preset DC coefficient 1: uses DCC coefficient
6.5.7
Zero-crossing volume enable
Bit R/W RST Name Description 1: volume adjustments only occur at digital zero-crossings 0: volume adjustments occur immediately
6
R/W
1
ZCE
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible.
6.5.8
Soft volume update enable
Bit 7 R/W R/W RST 1 Name SVE Description 1: volume adjustments ramp according to SVR settings 0: volume adjustments occur immediately
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STA333BW
Register description
6.6
Configuration register F (0x05)
D7 EAPD 0 D6 PWDN 1 D5 ECLE 0 D4 LDTE 1 D3 BCLE 1 D2 IDE 1 D1 OCFG1 0 D0 OCFG0 0
6.6.1
Output configuration
Bit 0 1 R/W R/W R/W RST 0 0 Name OCFG0 Selects the output configuration OCFG1 Description
Table 15.
OCFG[1:0]
Output configuration engine selection
Output configuration 2-channel (full-bridge) power, 2 channel data-out: 1A/1B 1A/1B 2A/2B 2A/2B Line out1 3A/3B Line out2 4A/4B Line out configuration determined by LOC register 2(half-bridge).1(full-bridge) on-board power: 1A 1A binary 0 2A 1B binary 90 3A/3B 2A/2B binary 45 1A/B 3A/B binary 0 2A/B 4A/B binary 90 2-channel (full-bridge) power, 1 channel DDX: 1A/1B 1A/1B 2A/2B 2A/2B 3A/3B 3A/3B EAPDEXT and TWARNEXT Active 1-channel mono-parallel: 3A 1A/1B w/ C3BO 45 3B 2A/2B w/ C3BO 45 1A/1B 3A/3B 2A/2B 4A/4B Config PIN
00
0
01
0
10
0
11
1
Note:
To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs.
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Register description
STA333BW
Figure 10. OCFG = 00 (default value)
Half Bridge
Figure 11. OCFG = 01
OUT1A
Channel 1
Half Bridge
Half Bridge
Channel 1
OUT1A
OUT1B OUT2A
Half Bridge
Half Bridge
Channel 2
OUT1B OUT2A
Channel 2
Half Bridge
Half Bridge
OUT2B
Channel 3
OUT3A OUT3B LPF
LineOut 1
Half Bridge
OUT2B
OUT4A OUT4B LPF
LineOut 2
Figure 12. OCFG = 10
Half Bridge
Figure 13. OCFG = 11
OUT1A
Half Bridge
OUT1A
Channel 1
Half Bridge
OUT1B OUT2A
Half Bridge
OUT1B
Channel 3
Half Bridge
Channel 2
Half Bridge
OUT2A
Half Bridge
OUT2B
Half Bridge
OUT2B
OUT3A OUT3B EAPD Power Device Channel 3
OUT3A OUT3B
Channel 1
OUT4A OUT4B
Channel 2
STA333BW can be configured to support different output configurations. For each PWM output channel a "PWM slot" is defined. PWM slot is always 1 / (8 x Fs) seconds length. The PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries.
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STA333BW Figure 14. STA333BW output mapping scheme.
DDX 1A OUT1A DDX 1B DDX 2A O UT1B OUT1A
Register description
OUT1B
DDXTM m odulator
DDX 2B DDX 3A DDX 3B DDX 4A DDX 4B O UT2B OUT2A
Power Bridge
OUT2A
OUT2B
REM AP
OUT3A
O UT3B
OUT4A
O UT4B
For each configuration the PWM from the digital driver are mapped in different way to the power stage: 2.0 channels, two full bridges (OCFG="00"):
" " " " " " " " " " " "
DDX1A ' OUT1A DDX1B ' OUT1B DDX2A ' OUT2A DDX2B ' OUT2B DDX3A ' OUT3A DDX3B ' OUT3B DDX4A ' OUT4A DDX4B ' OUT4B DDX1A/1B configured as ternary DDX2A/2B configured as ternary DDX3A/3B configured as lineout ternary DDX4A/4B configured as lineout ternary
On channel 3 line out (LOC bits = "00") the same datas as channel 1 processing are sent. On channel 4 line out (LOC bits = "00") the same datas as channel 2 processing are sent. In this configuration, no volume control or EQ have effect on channel 3 and 4. In this configuration the PWM slot phase is the following as shown in the next figures:
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Register description Figure 15. 2.0 channels (OCFG='00') PWM slots.
OUT1A OUT1B
STA333BW
OUT2A OUT2B
OUT3A OUT3B
OUT4A OUT4B
2.1 channels, two half bridges + one full bridge (OCFG="01"):
" " " " " " " " " " " "
DDX1A ' OUT1A DDX2A ' OUT1B DDX3A ' OUT2A DDX3B ' OUT2B DDX1A ' OUT3A DDX1B ' OUT3B DDX2A ' OUT4A DDX2B ' OUT4B DDX1A/1B configured as binary DDX2A/2B configured as binary DDX3A/3B configured as binary DDX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc...). On OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated. In this configuration the PWM slot phase is the following as shown in the next figures:
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STA333BW Figure 16. 2.1 channels (OCFG='01') PWM slots.
OUT1A OUT1B
Register description
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
2.1 channels, two fullbridge + one external full bridge (OCFG="10"):
" " " " " " " " " " " "
DDX1A ' OUT1A DDX1B ' OUT1B DDX2A ' OUT2A DDX2B ' OUT2B DDX3A ' OUT3A DDX3B ' OUT3B EAPD ' OUT4A TWARN OUT4B DDX1A/1B configured as ternary DDX2A/2B configured as ternary DDX3A/3B configured as ternary DDX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc...). On OUT4 channel the external bridge control signals are muxed. In this configuration the PWM slot phase is the following as shown in the next figures:
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Register description Figure 17. 2.1 channels (OCFG='10') PWM slots.
STA333BW
OUT1A OUT1B
OUT2A OUT2B
OUT3A OUT3B
6.6.2
Invalid input detect mute enable
Bit 2 R/W R/W RST 1 Name IDE Description Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid.
6.6.3
Binary output mode clock loss detection
Bit 3 R/W R/W RST 1 Name BCLE Description Binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
6.6.4
LRCK double trigger protection
Bit 4 R/W R/W RST 1 Name LDTE Description LRCLK double trigger protection enable
Actively prevents double trigger of LRCLK.
6.6.5
Auto EAPD on clock loss
Bit 5 R/W R/W RST 0 Name ECLE Description Auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
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STA333BW
Register description
6.6.6
IC power down
Bit 7 R/W R/W RST 1 Name PWDN Description 0: IC power down low-power condition 1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, then the master clock to all internal hardware expect the I2C block is gated. This places the IC in a very low power consumption state.
6.6.7
External amplifier power down
Bit 7 R/W R/W RST 0 Name EAPD Description 0: external power stage power down active 1: normal operation
The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state (disabled). This register also controls the DDX4B/EAPD output pin when OCFG = 10.
6.7
6.7.1
Volume control registers (0x06 to 0x0A)
Mute/line output configuration register
D7 LOC1 0 LOC[1:0] 00 01 10 D6 LOC0 0 D5 D4 D3 C3M 0 D2 C2M 0 D1 C1M 0 D0 MMUTE 0
Line output configuration Line output fixed, no volume, no EQ Line output variable, CH3 volume effects line output, no EQ Line output variable with EQ, CH3 volume effects line output
Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.
6.7.2
Master volume register
D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1
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Register description
STA333BW
6.7.3
Channel 1 volume
D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0
6.7.4
Channel 2 volume
D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0
6.7.5
Channel 3 / line output volume
D7 C3V7 0 D6 C3V6 1 D5 C3V5 1 D4 C3V4 0 D3 C3V3 0 D2 C3V2 0 D1 C3V1 0 D0 C3V0 0
The Volume structure of the STA333BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB. As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB. The Master Mute when set to 1 mutes all channels at once, whereas the individual channel mutes (CxM) mutes only that channel. Both the Master Mute and the Channel Mutes provide a "soft mute" with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate(~96 kHz). A "hard mute" can be obtained by commanding a value of all 1's (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than -80 dB is muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE=0, volume updates occur immediately. Table 16. Master volume offset as a function of MV[7:0]
Volume offset from channel value 0 dB -0.5 dB -1 dB ... -38 dB
MV[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01001100 (0x4C)
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STA333BW Table 16.
Register description Master volume offset as a function of MV[7:0] (continued)
Volume offset from channel value ... -127.5 dB Hard master mute
MV[7:0] ... 11111110 (0xFE) 11111111 (0xFF)
Table 17.
Channel volume as a function of CxV[7:0]
Volume +48 dB +47.5 dB +47 dB ... +0.5 dB 0 dB -0.5 dB ... -59.5 dB -60 dB -61 dB -62 dB ... -80 dB Hard channel mute ... Hard channel mute
CxV[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) ... 11010111 (0xD7) 11011000 (0xD8) 11011001 (0xD9) 11011010 (0xDA) ... 11101100 (0xEC) 11101101 (0xED) ... 11111111 (0xFF)
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Register description
STA333BW
6.8
6.8.1
Auto mode registers (0x0B and 0x0C)
AutoMode register 1 (0x0B)
D7 D6 D5 AMGC1 0 D4 AMGC2 0 D3 D2 D1 D0
Table 18.
AutoMode gain compression/limiters selection
Mode User programmable GC AC no clipping 2.1 AC limited clipping (10%) 2.1 DRC nighttime listening mode 2.1
AMGC[1:0] 00 01 10 11
6.8.2
AutoMode register 2 (0x0C)
D7 XO3 0 D6 XO2 0 D5 XO1 0 D4 XO0 0 D3 AMAM2 0 D2 AMAM1 0 D1 AMAM0 0 D0 AMAME 0
6.8.3
AM interference frequency switching
Bit R/W RST Name Description AutoMode AM Enable 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings
0
R/W
0
AMAME
Table 19.
AutoMode AM switching frequency selection
48 kHz / 96 kHz input Fs 0.535 MHz to 0.720 MHz 0.721 MHz to 0.900 MHz 0.901 MHz to 1.100 MHz 1.101 MHz to 1.300 MHz 1.301 MHz to 1.480 MHz 1.481 MHz to 1.600 MHz 1.601 MHz to 1.700 MHz 44.1 kHz / 88.2 kHz input Fs 0.535 MHz to 0.670 MHz 0.671 MHz to 0.800 MHz 0.801 MHz to 1.000 MHz 1.001 MHz to 1.180 MHz 1.181 MHz to 1.340 MHz 1.341 MHz to 1.500 MHz 1.501 MHz to 1.700 MHz
AMAM[2:0] 000 001 010 011 100 101 110
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STA333BW
Register description
6.8.4
Bass management crossover
Bit 4 5 6 7 R/W R/W R/W R/W R/W RST 0 0 0 0 Name XO0 XO1 XO2 XO3 Selects the bass-management crossover frequency. A 1st-order high-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed. Description
Table 20.
Bass management crossover frequency
Crossover frequency User-Defined 80 Hz 100 Hz 120 Hz 140 Hz 160 Hz 180 Hz 200 Hz 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Hz
XO[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
6.9
Channel configuration registers ( 0x0E to 0x10)
D7 C1OM1 0 D7 C2OM1 0 D6 C1OM0 0 D6 C2OM0 1 D5 C1LS1 0 D5 C2LS1 0 D4 C1LS0 0 D4 C2LS0 0 D3 C1BO 0 D3 C2BO 0 D2 C1VPB 0 D2 C2VPB 0 D1 C1EQBP 0 D1 C2EQBP 0 D0 C1TCB 0 D0 C2TCB 0
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Register description
STA333BW
D7 C3OM1 1
D6 C3OM0 0
D5 C3LS1 0
D4 C3LS0 0
D3 C3BO 0
D2 C3VPB 0
D1
D0
6.9.1
Tone control bypass
Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2. CxTCB: 0: perform tone control on channel X, normal operation 1: bypass tone control on channel X
6.9.2
EQ bypass
EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. CxEQBP: 0: perform EQ on channel X, normal operation 1: bypass EQ on channel X
6.9.3
Volume bypass
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
6.9.4
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is negative inverse. CxBO: 0: DDX tri-state output, normal operation 1: binary output
6.9.5
Limiter select
Limiter selection can be made on a per-channel basis according to the channel limiter select bits. Table 21.
.
Channel limiter mapping as a function of CxLS bits
Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2
CxLS[1:0] 00 01 10
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STA333BW
Register description
6.9.6
Output mapping
Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs. Table 22.
.
Channel output mapping as a function of CxOM bits
Channel x output source from Channel1 Channel 2 Channel 3
CxOM[1,0] 00 01 10
6.10
6.10.1
Tone control register (0x11)
Tone control
D7 TTC3 0 D6 TTC2 1 D5 TTC1 1 D4 TTC0 1 D3 BTC3 0 D2 BTC2 1 D1 BTC1 1 D0 BTC0 1
Table 23.
Tone control boost/cut as a function of BTC and TTC bits
Boost/Cut -12 dB -12 dB ... -4 dB -2 dB 0 dB +2 dB +4 dB ... +12 dB +12 dB +12 dB
BTC[3:0]/TTC[3:0] 0000 0001 ... 0111 0110 0111 1000 1001 ... 1101 1110 1111
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Register description
STA333BW
6.11
6.11.1
Dynamics control registers (0x12 to 0x15)
Limiter 1 attack/release rate
D7 L1A3 0 D6 L1A2 1 D5 L1A1 1 D4 L1A0 0 D3 L1R3 1 D2 L1R2 0 D1 L1R1 1 D0 L1R0 0
6.11.2
Limiter 1 attack/release threshold
D7 L1AT3 0 D6 L1AT2 1 D5 L1AT1 1 D4 L1AT0 0 D3 L1RT3 1 D2 L1RT2 0 D1 L1RT1 0 D0 L1RT0 1
6.11.3
Limiter 2 attack/release rate
D7 L2A3 0 D6 L2A2 1 D5 L2A1 1 D4 L2A0 0 D3 L2R3 1 D2 L2R2 0 D1 L2R1 1 D0 L2R0 0
6.11.4
Limiter 2 attack/release threshold
D7 L2AT3 0 D6 L2AT2 1 D5 L2AT1 1 D4 L2AT0 0 D3 L2RT3 1 D2 L2RT2 0 D1 L2RT1 0 D0 L2RT0 1
The STA333BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration Register F, bit 0 address 0x05. Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0dBFS is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. It is recommended in anti-clipping mode to set this to 0dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within STA333BW it is possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm.
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STA333BW
Register description The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past it's set value and therefore the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 18. Basic limiter and volume flow diagram
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Register description
STA333BW
Table 24.
LxA[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Limiter attack rate as a function of LxA bits
Attack Rate dB/ms 3.1584 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 Slow Fast
Table 25.
LxR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Limiter release rate as a function of LxR bits
Release Rate dB/ms 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 Slow Fast
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STA333BW
Register description
Anti-clipping mode
Table 26. Limiter attack threshold as a function of LxAT bits (AC-Mode).
AC(dB relative to FS) -12 -10 -8 -6 -4 -2 0 +2 +3 +4 +5 +6 +7 +8 +9 +10
Table 27.
Limiter release threshold as a function of LxRT bits (AC-Mode).
AC(dB relative to FS) - -29 dB -20 dB -16 dB -14 dB -12 dB -10 dB -8 dB -7 dB -6 dB -5 dB -4 dB -3 dB -2 dB -1 dB -0 dB
LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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Register description
STA333BW
Dynamic range compression mode
Table 28. Limiter attack threshold as a function of LxAT bits (DRC-Mode).
DRC(dB relative to Volume) -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 -10 -7 -4
Table 29.
Limiter release threshold as a as a function of LxRT bits (DRC-Mode).
DRC(db relative to Volume + LxAT) - -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB -15 dB -12 dB -9 dB -6 dB
LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
6.12
6.12.1
User-defined coefficient control registers (0x16 to 0x26)
Coefficient address register
D7 D6 D5 CFA5 0 D4 CFA4 0 D3 CFA3 0 D2 CFA2 0 D1 CFA1 0 D0 CFA0 0
6.12.2
Coefficient b1 data register bits 23:16
D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
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STA333BW
Register description
6.12.3
Coefficient b1 data register bits 15:8
D7 C1B15 0 D6 C1B14 0 D5 C1B13 0 D4 C1B12 0 D3 C1B11 0 D2 C1B10 0 D1 C1B9 0 D0 C1B8 0
6.12.4
Coefficient b1 data register bits 7:0
D7 C1B7 0 D6 C1B6 0 D5 C1B5 0 D4 C1B4 0 D3 C1B3 0 D2 C1B2 0 D1 C1B1 0 D0 C1B0 0
6.12.5
Coefficient b2 data register bits 23:16
D7 C2B23 0 D6 C2B22 0 D5 C2B21 0 D4 C2B20 0 D3 C2B19 0 D2 C2B18 0 D1 C2B17 0 D0 C2B16 0
6.12.6
Coefficient b2 data register bits 15:8
D7 C2B15 0 D6 C2B14 0 D5 C2B13 0 D4 C2B12 0 D3 C2B11 0 D2 C2B10 0 D1 C2B9 0 D0 C2B8 0
6.12.7
Coefficient b2 data register bits 7:0
D7 C2B7 0 D6 C2B6 0 D5 C2B5 0 D4 C2B4 0 D3 C2B3 0 D2 C2B2 0 D1 C2B1 0 D0 C2B0 0
6.12.8
Coefficient a1 data register bits 23:16
D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
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Register description
STA333BW
6.12.9
Coefficient a1 data register bits 15:8
D7 C3B15 0 D6 C3B14 0 D5 C3B13 0 D4 C3B12 0 D3 C3B11 0 D2 C3B10 0 D1 C3B9 0 D0 C3B8 0
6.12.10
Coefficient a1 data register bits 7:0
D7 C3B7 0 D6 C3B6 0 D5 C3B5 0 D4 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 C3B1 0 D0 C3B0 0
6.12.11
Coefficient a2 data register bits 23:16
D7 C4B23 0 D6 C4B22 0 D5 C4B21 0 D4 C4B20 0 D3 C4B19 0 D2 C4B18 0 D1 C4B17 0 D0 C4B16 0
6.12.12
Coefficient a2 data register bits 15:8
D7 C4B15 0 D6 C4B14 0 D5 C4B13 0 D4 C4B12 0 D3 C4B11 0 D2 C4B10 0 D1 C4B9 0 D0 C4B8 0
6.12.13
Coefficient a2 data register bits 7:0
D7 C4B7 0 D6 C4B6 0 D5 C4B5 0 D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0
6.12.14
Coefficient b0 data register bits 23:16
D7 C5B23 0 D6 C5B22 0 D5 C5B21 0 D4 C5B20 0 D3 C5B19 0 D2 C5B18 0 D1 C5B17 0 D0 C5B16 0
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STA333BW
Register description
6.12.15
Coefficient b0 data register bits 15:8
D7 C5B15 0 D6 C5B14 0 D5 C5B13 0 D4 C5B12 0 D3 C5B11 0 D2 C5B10 0 D1 C5B9 0 D0 C5B8 0
6.12.16
Coefficient b0 data register bits 7:0
D7 C5B7 0 D6 C5B6 0 D5 C5B5 0 D4 C5B4 0 D3 C5B3 0 D2 C5B2 0 D1 C5B1 0 D0 C5B0 0
6.12.17
Coefficient write/read control register
D7 D6 D5 D4 D3 RA 0 D2 R1 0 D1 WA 0 D0 W1 0
Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA333BW via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM. Note: The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.
Reading a coefficient from RAM
1. 2. 3. 4. 5. Write 6-bits of address to I2C register 0x16. Write 1 to R1 bit in I2C address 0x26. Read top 8-bits of coefficient in I2C address 0x17. Read middle 8-bits of coefficient in I2C address 0x18. Read bottom 8-bits of coefficient in I2C address 0x19.
Reading a set of coefficients from RAM
1. 2. 3. 4. 5. 6. 7. 8. Write 6-bits of address to I2C register 0x16. Write 1 to RA bit in I2C address 0x26. Read top 8-bits of coefficient in I2C address 0x17. Read middle 8-bits of coefficient in I2C address 0x18. Read bottom 8-bits of coefficient in I2C address 0x19. Read top 8-bits of coefficient b2 in I2C address 0x1A. Read middle 8-bits of coefficient b2 in I2C address 0x1B. Read bottom 8-bits of coefficient b2 in I2C address 0x1C.
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Register description 9. Read top 8-bits of coefficient a1 in I2C address 0x1D.
STA333BW
10. Read middle 8-bits of coefficient a1 in I2C address 0x1E. 11. Read bottom 8-bits of coefficient a1 in I2C address 0x1F. 12. Read top 8-bits of coefficient a2 in I2C address 0x20. 13. Read middle 8-bits of coefficient a2 in I2C address 0x21. 14. Read bottom 8-bits of coefficient a2 in I2C address 0x22. 15. Read top 8-bits of coefficient b0 in I2C address 0x23. 16. Read middle 8-bits of coefficient b0 in I2C address 0x24. 17. Read bottom 8-bits of coefficient b0 in I2C address 0x25.
Writing a single coefficient to RAM
1. 2. 3. 4. 5. Write 6-bits of address to I2C register 0x16. Write top 8-bits of coefficient in I2C address 0x17. Write middle 8-bits of coefficient in I2C address 0x18. Write bottom 8-bits of coefficient in I2C address 0x19. Write 1 to W1 bit in I2C address 0x26.
Writing a set of coefficients to RAM
1. 2. 3. 4. 5. 6. 7. 8. 9. Write 6-bits of starting address to I2C register 0x16. Write top 8-bits of coefficient b1 in I2C address 0x17. Write middle 8-bits of coefficient b1 in I2C address 0x18. Write bottom 8-bits of coefficient b1 in I2C address 0x19. Write top 8-bits of coefficient b2 in I2C address 0x1A. Write middle 8-bits of coefficient b2 in I2C address 0x1B. Write bottom 8-bits of coefficient b2 in I2C address 0x1C. Write top 8-bits of coefficient a1 in I2C address 0x1D. Write middle 8-bits of coefficient a1 in I2C address 0x1E.
10. Write bottom 8-bits of coefficient a1 in I2C address 0x1F. 11. Write top 8-bits of coefficient a2 in I2C address 0x20. 12. Write middle 8-bits of coefficient a2 in I2C address 0x21. 13. Write bottom 8-bits of coefficient a2 in I2C address 0x22. 14. Write top 8-bits of coefficient b0 in I2C address 0x23. 15. Write middle 8-bits of coefficient b0 in I2C address 0x24. 16. Write bottom 8-bits of coefficient b0 in I2C address 0x25. 17. Write 1 to WA bit in I2C address 0x26. The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA333BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
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STA333BW
Register description
6.12.18
User-defined EQ
The STA333BW provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] to 2(a1/2)Y[n-1] - a2Y[n-2] = b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808). Coefficients stored in the User Defined Coefficient RAM are referenced in the following manner: CxHy0 = b1/2 CxHy1 = b2 CxHy2 = -a1/2 CxHy3 = -a2 CxHy4 = b0/2 where x represents the channel and the y the biquad number. For example C2H41 is the b2 coefficient in the fourth biquad for channel 2. Additionally, the STA333BW allows specification of a high-pass filter (processing channels 1 and 2) and a lo-pass filter (processing channel 3) to be used for bass-management crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation noted above. They are loaded into the C12H0-4 and C3Hy0-4 areas of RAM noted in Table 30. By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b0/2 coefficient which is set to 0x400000 (representing 0.5)
6.12.19
Pre-scale
The STA333BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. All channels can use the channel 1 pre-scale factor by setting the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.
6.12.20
Post-scale
The STA333BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel 1 post-scale factor by setting the post-scale link bit. By default, all post-scale factors are set to 0x7FFFFF. When Line output is being utilized, channel 3 post-scale will affect both channels 3 and 4.
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Register description
STA333BW
6.12.21
Over-current post-scale
The STA333BW provides a simple mechanism for reacting to over-current detection in the power-block. When the ocwarn input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides 3 dB of output attenuation when ocwarn is asserted. The amount of attenuation to be applied in this situation can be adjusted by modifying the Over-current Post-scale value. As with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, the over-current post-scale factor is set to 0x5A9DF7. Once the over-current attenuation is applied, it remains until the device is reset. Table 30. RAM block for biquads, mixing, scaling and bass management
Coefficient C1H10(b1/2) C1H11(b2) Channel 1, Biquad 1 C1H12(a1/2) C1H13(a2) C1H14(b0/2) Channel 1, Biquad 2 ... Channel 1, Biquad 4 Channel 2, Biquad 1 0x15 ... 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 Channel 1, Pre-Scale Channel 2, Pre-Scale Channel 1, Post-Scale Channel 2, Post-Scale Lo-Pass 2nd Order Filter for XO=000 Hi-Pass 2nd Order Filter for XO=000 ... Channel 2, Biquad 4 C2H11 ... C2H44 C12H0(b1/2) C12H1(b2) C12H2(a1/2) C12H3(a2) C12H4(b0/2) C3H0(b1/2) C3H1(b2) C3H2(a1/2) C3H3(a2) C3H4(b0/2) C1PreS C2PreS C1PstS C2PstS 0x000000 ... 0x400000 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 0x000000 0x000000 0x000000 0x400000 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x7FFFFF C1H20 ... C1H44 C2H10 Default 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 ... 0x400000 0x000000
Index (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 ... 0x13 0x14
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STA333BW Table 30.
Register description RAM block for biquads, mixing, scaling and bass management
Coefficient Channel 3, Post-Scale TWARN/OC- Limit Channel 1, Mix 1 Channel 1, Mix 2 Channel 2, Mix 1 Channel 2, Mix 2 Channel 3, Mix 1 Channel 3, Mix 2 UNUSED UNUSED C3PstS TWOCL C1MX1 C1MX2 C2MX1 C2MX2 C3MX1 C3MX2 Default 0x7FFFFF 0x5A9DF7 0x7FFFFF 0x000000 0x000000 0x7FFFFF 0x400000 0x400000
Index (Hex) 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
6.13
Variable max power correction registers (0x27 to 0x28)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.
D7 MPCC15 0 D7 MPCC7 1 D6 MPCC14 0 D6 MPCC6 1 D5 MPCC13 0 D5 MPCC5 0 D4 MPCC12 1 D4 MPCC4 0 D3 MPCC11 1 D3 MPCC3 0 D2 MPCC10 0 D2 MPCC2 0 D1 MPCC9 1 D1 MPCC1 0 D0 MPCC8 0 D0 MPCC0 0
6.14
Variable distortion compensation registers (0x29 to 0x2A)
DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.
D7 DCC15 1 D6 DCC14 1 D5 DCC13 1 D4 DCC12 1 D3 DCC11 0 D2 DCC10 0 D1 DCC9 1 D0 DCC8 1
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Register description
STA333BW
D7 DCC7 0
D6 DCC6 0
D5 DCC5 1
D4 DCC4 1
D3 DCC3 0
D2 DCC2 0
D1 DCC1 1
D0 DCC0 1
6.15
Fault detect recovery constant registers (0x2B to 0x2C)
FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is ~.083 ms. The default value of 0x000C specifies ~.1 mS.
D7 FDRC15 0 D7 FDRC7 0 D6 FDRC14 0 D6 FDRC6 0 D5 FDRC13 0 D5 FDRC5 0 D4 FDRC12 0 D4 FDRC4 0 D3 FDRC11 0 D3 FDRC3 1 D2 FDRC10 0 D2 FDRC2 1 D1 FDRC9 0 D1 FDRC1 0 D0 FDRC8 0 D0 FDRC0 0
6.16
Device status register (0x2D)
D7 PLLUL D6 FAULT D5 UVFAULT D4 OVFAULT D3 OCFAULT D2 OCWARN D1 TFAULT D0 TWARN
This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL='1' means that the PLL is not locked.
" " " " " " " "
PLLUL: 0 = PLL locked, 1= PLL not locked. FAULT: 0 = fault detected on power bridge, 1 = normal operation UVFAULT: 0 = VCC1, VCC2 internally detected < under-voltage threshold. OVFAULT: 0 = VCC1, VCC2 internally detected > over-voltage threshold. OCFAULT: 0 = over-current fault detected OCWARN: 0 = over-current warning. TFAULT: 0 = thermal fault, junction temperature over-limit detection. TWARN: 0 = thermal warning, junction temperature is close to the fault condition.
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STA333BW
Application
7
7.1
Application
Application scheme for power supplies
Here in the next figure the typical application scheme for STA333BW concerning the power supplies. A particular care has to be devoted to the layout of the PCB. In particular the 3.3 resistors on the digital supplies (VDD_DIG) have to be put as close as possible to the device. This is to avoid any unwanted oscillation on the digital portion of the device due to the PCB track inductance. The same rule must also be applied to all the decoulpling capacitors in order to limit any kind of voltage spikes on all the supplies. Figure 19. Application scheme for power supplies
3R3 1 2 3 4 100nF 1uF 35V OUT2B 5 6 7 8 100nF 100nF OUT2A VCC OUT1B 9 10 11 12 1uF 35V OUT1A 100nF 13 14 15 16 DDX3B DDX3A 17 18 1000uF 35V + GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A GND_REG VDD CONFIG DDX3B DDX3A VDD_DIG GND_DIG SCL SDA INT_LINE RESET SDI LRCKI BICKI XTI PLL_GND FILTER_PLL VDD_PLL PWRDN GND_DIG VDD_DIG TWARN/4A EAPD/4B 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 3R3 TW EAPD 100nF PWDN
GND_DIG
3V3 100nF 3V3
SCL SDA INTL
GND_DIG
10K
RESET DATA LRCKI BICKI XTI
BEAD GND_DIG
1nF
RESET
PLL_FILT
100nF
BEAD
PLL_GND
GND_DIG
3V3
3V3
7.2
PLL filter schematic
It is recommended to use the below scheme and values for the PLL loop filter to achieve the best performances from the device in general application. Please be noted that the ground of this filter scheme has to be conncted to the ground of the PLL without any resistive path. Concerning the component values, please take into acount that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter.
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Application Figure 20. PLL application scheme.
FILTER_PLL
STA333BW
2K2 680pF
4.7nF
BEAD
100pF
GND_DIG
PLL_GND
7.3
Typical output configuration
Here after the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other possible output configuration recommended schematics. Figure 21. Output configuration for stereo BTL mode
22uH OUT1A 100nF
6.2 22
100nF 470nF 100nF LEFT
330pF
6.2
100nF OUT1B 22uH
22uH OUT2A 100nF
6.2 22
100nF 470nF 100nF RIGHT
330pF
6.2
100nF OUT2B 22uH
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STA333BW
Package thermal characteristics
8
Package thermal characteristics
Using a double-layer PCB the thermal resistance junction to ambient with 2 copper ground area of 3x3 cm and with 16 via holes (see Figure 22) is 24 C/W in natural air convection. The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. The estimated maximum dissipated power for the STA333BW is: 2 x 20 W into 8 , 18 V 2 x 10 W + 1 x 20 W into 4 , 8 , 18 V Pd max ~ 4 W Pd max < 5 W
Figure 22. Double layer PCB Rth j-amb with 2 GND copper area and with 16 via holes
Figure 23 shows the power derating curve for the PSSO36 package with PCB copper areas of 2 x 2 cm and 3 x 3 cm. Figure 23. PSSO36 power derating curve
Pd (W)
8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 120 140 160
Tamb ( C)
Copper Area 2x2 cm and via holes Copper Area 3x3 cm and via holes STA333BW PSSO36
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Package information
STA333BW
9
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 24. PowerSSO-36 (slug-up) mechanical data and package dimensions
DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h k L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.5 8.5 2.3 0.10 0.06 10.50 0.40 5 0.55 4.3 10 1.2 0.8 2.9 3.65 1.0 4.1 6.5 4.7 7.3 0.161 0.256 0.047 0.031 0.114 0.144 0.039 0.185 0.287 0.90 0.022 0.169 10 mm TYP. MAX. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.019 0.335 0.090 0.004 0.002 0.413 0.016 5 0.035 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 0.299
OUTLINE AND MECHANICAL DATA
10.10
0.398
PowerSSO-36 (slug-down)
(1) "D" and "E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006")
A2
A
hx45u
G
LEAD COPLANARITY
A
D
e
stand-off
a1
T
Y M
Gauge plane 0.25
L
O
E
H
F
U
B
0.1 M A B
b e3
S
BOTTOM VIEW
X
7587131 A
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k
c
Q
STA333BW
Revision history
10
Revision history
Table 31.
Date 11-Apr-2006
Document revision history
Revision 1 Initial release. Added: Electrical specifications, digital section Power on sequence Processing data path Application Improved: Pin description Absolute maximum ratings Recommended operative conditions Output configuration Device status register Changes
26-Jul-2007
2
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STA333BW
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